Historically, one of the most important advantages of bipolar transistor technology has been its ability to drive large resistive and capacitive loads with relatively small device geometries. For instance, a typical emitter coupled logic gate comprises an emitter coupled logic stage coupled to a transistor emitter-follower output stage which restores DC levels. The emitter-follower output stage sources output current at the output of the ECL gate that is an exponential function of the emitter-base voltage of the output transistor. High fanout operation is possible because of the high input impedance of the emitter coupled logic gate and the low output impedance of the emitter-follower output stage. Early conventional emitter-follower output stages typically included a resistor coupled as a "pull-down" device between the output of the ECL gate and the negative power supply rail which sets the quiescent current in the emitter-follower output stage. A problem occurs when such prior art ECL gates are operated into large capacitive loads which must be discharged as the output of the gate switches from a first logic level to a second logic level. In prior art ECL gates, the discharge current must flow through the resistor to the negative supply rail of the gate. Since the resistor is much larger in value than the "on" resistance of the emitter-follower transistor, discharge of the capacitor is much slower than the charge thereof since discharge is at a near constant rate determined by the resistor. Hence, the input logic signal applied to the subsequent gate is skewed. This is highly undesirable because of the added difficulty in designing the remaining circuitry due to the skewed edges.
To decrease the discharge time, the value of the resistor coupled to the emitter follower stage of the ECL gate can be made smaller. However, this results in a undesirable increase in quiescent power dissipation since the quiescent current flowing through the emitter-follower output stage is increased.
Another previously known driver circuit includes a "pull-down" PNP transistor having an emitter coupled to the output terminal, a collector coupled to the negative power supply rail, and a base coupled to a current path driven by the same signal driving the emitter follower. However, present technology is unable to provide a process for creating a PNP transistor of sufficient quality for competitive performance.
Yet another previously known driver circuit includes a "pull-down" NPN transistor having a collector connected to the output terminal, an emitter connected to the negative power supply rail, and a base coupled by a capacitor to an inverse signal to that driving the emitter follower. This circuit produces a high discharge current and a low standby current, however the discharge current is not proportional to the load capacitance.
Another previously known driver circuit is disclosed in U.S. Pat. No. 4,675,554 that is similar to the previously mentioned circuit.
Still another previously known driver circuit is disclosed in U.S. Pat. No. 4,687,953, wherein a dynamic ECL transient driver circuit is disclosed having a current enhancement portion for increasing the current to the base of the "pull-down" transistor. The current enhancement portion comprises differentially connected first and second transistors having their collectors coupled to the output terminal and their emitters coupled to the negative supply voltage rail by a current source. The base of the first transistor is connected to a current source voltage and the base of the second transistor is connected to its own collector and the base of the "pull-down" transistor by a resistor. Additionally, a capacitor is coupled between the base of the second transistor and the base of a transistor sourcing current to the output terminal. The discharge current of this circuit is not proportional to the load capacitance.
In order to utilize bipolar ECL gates in complex logic circuits, the static power requirement of the ECL gate needs to be reduced without sacrificing speed. Additionally, the bipolar ECL gates must be able to provide transient source and sink currents such that large capacitive loads can be driven at high speed while at the same time minimizing the quiescent power dissipation of the ECL gates.
Thus, what is needed is a ECL transient driver circuit that discharges capacitive load at the output of an emitter follower with a pulse whose amplitude and duration is determined by the charge on the load.